SAT-Based Scalable Formal Verification Solutions (Integrated Circuits and Systems) - encuadernado, tapa blanda
2007, ISBN: 9780387691664
Springer, Gebundene Ausgabe, Auflage: 2007, 360 Seiten, Publiziert: 2007-05-22T00:00:01Z, Produktgruppe: Buch, Hersteller-Nr.: 22587001, 1.55 kg, CAD & CAM, Grafik & Multimedia, Computer … Más…
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2007, ISBN: 0387691669
2007 Gebundene Ausgabe EDV / Theorie / Software-Entw. / Software Engineering, Elektrotechnik, Computer-Aided Design (CAD), algorithms; complexity; computer-aideddesign(CAD); designproce… Más…
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ISBN: 9780387691664
by Malay Ganai; Aarti Gupta, PRINT ISBN: 9780387691664 E-TEXT ISBN: 9780387691671 Springer Nature eBook Other pricing structure might be available at vitalsource.com., Springer
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2007, ISBN: 9780387691664
[PU: Springer US], Neubindung 3487105/12, DE, [SC: 0.00], gebraucht; sehr gut, gewerbliches Angebot, 2007, Banküberweisung, Kreditkarte, PayPal, Klarna-Sofortüberweisung, International sh… Más…
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2007, ISBN: 9780387691664
[PU: Springer US], Neubindung 3487105/12, DE, [SC: 0.00], gebraucht; sehr gut, gewerbliches Angebot, 2007, Banküberweisung, PayPal, Klarna-Sofortüberweisung, Internationaler Versand
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SAT-Based Scalable Formal Verification Solutions (Integrated Circuits and Systems) - encuadernado, tapa blanda
2007, ISBN: 9780387691664
Springer, Gebundene Ausgabe, Auflage: 2007, 360 Seiten, Publiziert: 2007-05-22T00:00:01Z, Produktgruppe: Buch, Hersteller-Nr.: 22587001, 1.55 kg, CAD & CAM, Grafik & Multimedia, Computer … Más…
Gupta, Aarti; Ganai, Malay:
SAT-Based Scalable Formal Verification Solutions - encuadernado, tapa blanda2007, ISBN: 0387691669
2007 Gebundene Ausgabe EDV / Theorie / Software-Entw. / Software Engineering, Elektrotechnik, Computer-Aided Design (CAD), algorithms; complexity; computer-aideddesign(CAD); designproce… Más…
ISBN: 9780387691664
by Malay Ganai; Aarti Gupta, PRINT ISBN: 9780387691664 E-TEXT ISBN: 9780387691671 Springer Nature eBook Other pricing structure might be available at vitalsource.com., Springer
2007, ISBN: 9780387691664
[PU: Springer US], Neubindung 3487105/12, DE, [SC: 0.00], gebraucht; sehr gut, gewerbliches Angebot, 2007, Banküberweisung, Kreditkarte, PayPal, Klarna-Sofortüberweisung, International sh… Más…
2007, ISBN: 9780387691664
[PU: Springer US], Neubindung 3487105/12, DE, [SC: 0.00], gebraucht; sehr gut, gewerbliches Angebot, 2007, Banküberweisung, PayPal, Klarna-Sofortüberweisung, Internationaler Versand
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Detalles del libro - SAT-Based Scalable Formal Verification Solutions (Integrated Circuits and Systems)
EAN (ISBN-13): 9780387691664
ISBN (ISBN-10): 0387691669
Tapa dura
Tapa blanda
Año de publicación: 2007
Editorial: Springer
330 Páginas
Peso: 0,703 kg
Idioma: eng/Englisch
Libro en la base de datos desde 2007-11-11T17:18:47+01:00 (Madrid)
Página de detalles modificada por última vez el 2023-08-03T13:26:57+02:00 (Madrid)
ISBN/EAN: 0387691669
ISBN - escritura alterna:
0-387-69166-9, 978-0-387-69166-4
Mode alterno de escritura y términos de búsqueda relacionados:
Autor del libro: malay, mala gupta, jameson
Título del libro: sat based scalable formal verification solutions, integrated circuits
Datos del la editorial
Autor: Malay Ganai; Aarti Gupta
Título: Integrated Circuits and Systems; SAT-Based Scalable Formal Verification Solutions
Editorial: Springer; Springer US
330 Páginas
Año de publicación: 2007-05-22
New York; NY; US
Idioma: Inglés
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
Available
XXX, 330 p. 118 illus.
BB; Hardcover, Softcover / Informatik, EDV/Anwendungs-Software; Computer-Aided Design (CAD); Verstehen; algorithms; complexity; computer-aided design (CAD); design process; model; modeling; Computer-Aided Engineering (CAD, CAE) and Design; Electronic Circuits and Systems; Electrical and Electronic Engineering; Schaltkreise und Komponenten (Bauteile); Elektrotechnik; BC
Design Verification Challenges.- Design Verification Challenges.- Background.- Basic Infrastructure.- Efficient Boolean Representation.- Hybrid DPLL-Style SAT Solver.- Falsification.- SAT-Based Bounded Model Checking.- Distributed SAT-Based BMC.- Efficient Memory Modeling in BMC.- BMC for Multi-Clock Systems.- Proof Methods.- Proof by Induction.- Unbounded Model Checking.- Abstraction/Refinement.- Proof-Based Iterative Abstraction.- Verification Procedure.- SAT-Based Verification Framework.- Synthesis for Verification.Describes SAT-based model checking approaches and gives engineering details on what makes model checking practical Techniques covered can be synergistically combined into a scalabe solution Focuses on engineering design and not mathematics Includes supplementary material: sn.pub/extras
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