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Minimizing and Exploiting Leakage in VLSI Design / Nikhil Jayakumar (u. a.) / Buch / XXVII / Englisch / 2009 / Springer US / EAN 9781441909497 - Jayakumar, Nikhil
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Jayakumar, Nikhil:

Minimizing and Exploiting Leakage in VLSI Design / Nikhil Jayakumar (u. a.) / Buch / XXVII / Englisch / 2009 / Springer US / EAN 9781441909497 - encuadernado, tapa blanda

2009, ISBN: 9781441909497

[ED: Gebunden], [PU: Springer US], Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupl… Más…

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Minimizing and Exploiting Leakage in VLSI Design / Nikhil Jayakumar (u. a.) / Buch / XXVII / Englisch / 2009 / Springer US / EAN 9781441909497 - Jayakumar, Nikhil
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Jayakumar, Nikhil:

Minimizing and Exploiting Leakage in VLSI Design / Nikhil Jayakumar (u. a.) / Buch / XXVII / Englisch / 2009 / Springer US / EAN 9781441909497 - encuadernado, tapa blanda

2009, ISBN: 9781441909497

[ED: Gebunden], [PU: Springer US], Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupl… Más…

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Minimizing and Exploiting Leakage in VLSI Design - Jayakumar, Nikhil, Paul, Suganth, Garg, Rajesh
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Jayakumar, Nikhil, Paul, Suganth, Garg, Rajesh:
Minimizing and Exploiting Leakage in VLSI Design - libro usado

2009

ISBN: 9781441909497

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Minimizing and Exploiting Leakage in VLSI Design - Jayakumar, Nikhil; Paul, Suganth; Garg, Rajesh
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Jayakumar, Nikhil; Paul, Suganth; Garg, Rajesh:
Minimizing and Exploiting Leakage in VLSI Design - encuadernado, tapa blanda

2009, ISBN: 1441909494

2010 Gebundene Ausgabe Technology & Industrial Arts, COMPUTERS / CAD-CAM, COMPUTERS / Logic Design, TECHNOLOGY & ENGINEERING / Electronics / Circuits / General, Schaltkreise und Kompone… Más…

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Jayakumar, Nikhil, and Paul, Suganth, and Garg, Rajesh:
Minimizing and Exploiting Leakage in VLSI Design - encuadernado, tapa blanda

2009, ISBN: 9781441909497

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Minimizing and Exploiting Leakage in VLSI Design
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ISBN:

1441909494


Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.

Detalles del libro - Minimizing and Exploiting Leakage in VLSI Design


EAN (ISBN-13): 9781441909497
ISBN (ISBN-10): 1441909494
Tapa dura
Tapa blanda
Año de publicación: 2010
Editorial: Springer-Verlag New York Inc.
214 Páginas
Peso: 0,510 kg
Idioma: eng/Englisch

Libro en la base de datos desde 2007-12-17T05:54:55+01:00 (Madrid)
Página de detalles modificada por última vez el 2024-02-11T22:40:42+01:00 (Madrid)
ISBN/EAN: 1441909494

ISBN - escritura alterna:
1-4419-0949-4, 978-1-4419-0949-7
Mode alterno de escritura y términos de búsqueda relacionados:
Autor del libro: anu garg, sunil, gula, gulat
Título del libro: vlsi, mini design

Datos del la editorial

Autor: Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Título: Minimizing and Exploiting Leakage in VLSI Design
Editorial: Springer; Springer US
214 Páginas
Año de publicación: 2009-12-03
New York; NY; US
Impreso en
Idioma: Inglés
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
POD
XXVII, 214 p.

BB; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; ASIC; EDA; Electronic Design Automation; Leakage; Low Power Design; Sub-threshold logic; Transistor; VLSI; VLSI Design; integrated circuit; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Computer-Aided Design (CAD); BC

Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes).
Provides a variety of approaches to control and exploit leakage Examines the issues with implementing sub-threshold logic and describes techniques to tackle these issues Presents a new, practical self-compensated, closed loop approach to controlling leakage, via sub-threshold circuits, which yields upwards of 20X power savings
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