- 5 Resultados
precio mínimo: € 107,09, precio máximo: € 130,89, precio promedio: € 113,19
1
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Pedir
por Springer.com
€ 107,09
Pedir
Detalles y envío
Enlace patrocinado
Nikhil Jayakumar; Suganth Paul; Rajesh Garg:

Minimizing and Exploiting Leakage in VLSI Design - libro nuevo

ISBN: 9781441909503

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for p… Más…

  - new in stock. Gastos de envío:zzgl. Versandkosten., más gastos de envío
cerrar (X)
2
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Pedir
por Springer.com
€ 107,09
Pedir
Detalles y envío
Enlace patrocinado

Nikhil Jayakumar; Suganth Paul; Rajesh Garg:

Minimizing and Exploiting Leakage in VLSI Design - libro nuevo

ISBN: 9781441909503

Engineering; Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design ASIC, EDA, Electronic Design Automation, Leakage, Low Power Design, Sub-threshold logic, Transistor, VL… Más…

  - This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Gastos de envío:zzgl. Versandkosten., más gastos de envío
cerrar (X)
3
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Pedir
por Springer.com
€ 107,09
Pedir
Detalles y envío
Enlace patrocinado
Nikhil Jayakumar; Suganth Paul; Rajesh Garg:
Minimizing and Exploiting Leakage in VLSI Design - libro nuevo

ISBN: 9781441909503

Engineering; Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design ASIC, EDA, Electronic Design Automation, Leakage, Low Power Design, Sub-threshold logic, Transistor, VL… Más…

  - This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Gastos de envío:zzgl. Versandkosten., más gastos de envío
cerrar (X)
4
Minimizing and Exploiting Leakage in VLSI Design - Hugo Pinto
Pedir
por hive.co.uk
£ 101,58
(aprox. € 113,78)
Pedir
Detalles y envío
Enlace patrocinado
Hugo Pinto:
Minimizing and Exploiting Leakage in VLSI Design - libro nuevo

ISBN: 9781441909503

This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the s… Más…

  - No. 9781441909503. Gastos de envío:Instock, Despatched same working day before 3pm, zzgl. Versandkosten., más gastos de envío
cerrar (X)
5
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Pedir
por lehmanns.de
€ 130,89
Envío: € 0,001
Pedir
Detalles del proveedor
Enlace patrocinado
Nikhil Jayakumar; Suganth Paul; Rajesh Garg:
Minimizing and Exploiting Leakage in VLSI Design - Primera edición

2009, ISBN: 9781441909503

[ED: 1], Auflage, eBook Download (PDF), eBooks, [PU: Springer-Verlag]

Gastos de envío:Download sofort lieferbar, , Versandkostenfrei innerhalb der BRD. (EUR 0.00)
cerrar (X)
1Dado que algunas plataformas no nos comunican las condiciones de envío y éstas pueden depender del país de entrega, del precio de compra, del peso y tamaño del artículo, de una posible membresía a la plataforma, de una entrega directa por parte de la plataforma o a través de un tercero (Marketplace), etc., es posible que los gastos de envío indicados por eurolibro/terralibro no concuerden con los de la plataforma ofertante.

Datos bibliográficos del mejor libro coincidente

Detalles del libro
Minimizing and Exploiting Leakage in VLSI Design
Autor:
Título:
ISBN:

1441909508

Detalles del libro - Minimizing and Exploiting Leakage in VLSI Design


EAN (ISBN-13): 9781441909503
ISBN (ISBN-10): 1441909508
Año de publicación: 2009
Editorial: Springer-Verlag
214 Páginas
Idioma: eng/Englisch

Libro en la base de datos desde 2012-03-25T23:47:37+02:00 (Madrid)
Página de detalles modificada por última vez el 2020-03-10T20:48:44+01:00 (Madrid)
ISBN/EAN: 1441909508

ISBN - escritura alterna:
1-4419-0950-8, 978-1-4419-0950-3
Mode alterno de escritura y términos de búsqueda relacionados:
Autor del libro: sunil, garg
Título del libro: vlsi, mini design

Datos del la editorial

Autor: Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Título: Minimizing and Exploiting Leakage in VLSI Design
Editorial: Springer; Springer US
214 Páginas
Año de publicación: 2009-12-02
New York; NY; US
Idioma: Inglés
106,99 € (DE)
110,00 € (AT)
130,00 CHF (CH)
Available
XXVII, 214 p.

EA; E107; eBook; Nonbooks, PBS / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; ASIC; EDA; Electronic Design Automation; Leakage; Low Power Design; Sub-threshold logic; Transistor; VLSI; VLSI Design; integrated circuit; C; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Engineering; Computer-Aided Design (CAD); BC

Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes).
Provides a variety of approaches to control and exploit leakage Examines the issues with implementing sub-threshold logic and describes techniques to tackle these issues Presents a new, practical self-compensated, closed loop approach to controlling leakage, via sub-threshold circuits, which yields upwards of 20X power savings

Más, otros libros, que pueden ser muy parecidos a este:

Último libro similar:
9781441909497 Minimizing and Exploiting Leakage in VLSI Design (Jayakumar, Nikhil; Paul, Suganth; Garg, Rajesh)

< para archivar...