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On and Off-Chip Crosstalk Avoidance in VLSI Design / Chunjie Duan (u. a.) / Buch / XXIV / Englisch / 2010 / Springer US / EAN 9781441909466 - encuadernado, tapa blanda

2010, ISBN: 9781441909466

[ED: Gebunden], [PU: Springer US], On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many chall… Más…

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ISBN: 9781441909466

Deep Sub-Micron (DSM) processes present many changes to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is crosstalk, which becomes significant with … Más…

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Duan, Chunjie und Brock J. LaMeres:
On and Off-Chip Crosstalk Avoidance in VLSI Design 2010 - Primera edición

2010

ISBN: 9781441909466

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Duan, Chunjie und Brock J. LaMeres:
On and Off-Chip Crosstalk Avoidance in VLSI Design - Primera edición

2010, ISBN: 9781441909466

[PU: Springer US], Neubindung, 1. Auflage 2010, Buchschnitt leicht verkürzt 5974541/12, DE, [SC: 0.00], gebraucht; sehr gut, gewerbliches Angebot, 2010, Banküberweisung, PayPal, Klarna-So… Más…

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On and Off-Chip Crosstalk Avoidance in VLSI Design - Duan, Chunjie und Brock J. LaMeres
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Duan, Chunjie und Brock J. LaMeres:
On and Off-Chip Crosstalk Avoidance in VLSI Design - Primera edición

2010, ISBN: 9781441909466

[PU: Springer US], Neubindung, 1. Auflage 2010, Buchschnitt leicht verkürzt 5974541/12, DE, [SC: 0.00], gebraucht; sehr gut, gewerbliches Angebot, 2010, PayPal, Klarna-Sofortüberweisung, … Más…

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Detalles del libro
On and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan Author
Autor:
Título:
ISBN:

144190946X


Deep Sub-Micron (DSM) processes present many changes to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is crosstalk, which becomes significant with shrinking feature sizes of VLSI fabrication processes. The presence of crosstalk greatly limits the speed and increases the power consumption of the IC design. This book focuses on crosstalk avoidance with bus encoding, one of the techniques that selectively mitigates the impact of crosstalk and improves the speed and power consumption of the bus interconnect. This technique encodes data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. TOC:Introduction on On-Chip Crosstalk Avoidance. Preliminaries to On-Chip Crosstalk. Memoryless Crosstalk Avoidance Codes. CODEC Designs for Memoryless Crosstalk Avoidance Codes. Memory-based Crosstalk Avoidance Codes. Multi-valued Logic Crosstalk Avoidance Codes. Introduction to Off-Chip Crosstalk. Package Construction and Electrical Modeling. Preliminaries and Terminology. Analytical Model for Off-Chip Bus Performance. Optimal Bus Sizing. Bus Expansion Encoder. Bus Stuttering Encoder. Impedance Compensation. Future Trends and Applications. Summary of Off-Chip Crosstalk Avoidance.

Detalles del libro - On and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan Author


EAN (ISBN-13): 9781441909466
ISBN (ISBN-10): 144190946X
Tapa dura
Año de publicación: 2010
Editorial: Springer US Core >2 >T
240 Páginas
Peso: 0,552 kg
Idioma: eng/Englisch

Libro en la base de datos desde 2008-10-25T09:24:15+02:00 (Madrid)
Página de detalles modificada por última vez el 2024-03-01T20:27:19+01:00 (Madrid)
ISBN/EAN: 144190946X

ISBN - escritura alterna:
1-4419-0946-X, 978-1-4419-0946-6
Mode alterno de escritura y términos de búsqueda relacionados:
Autor del libro: sunil, lamer, lamé, duan, brock lameres
Título del libro: chip, talk talk, vlsi, off, design design

Datos del la editorial

Autor: Chunjie Duan; Brock J. LaMeres
Título: On and Off-Chip Crosstalk Avoidance in VLSI Design
Editorial: Springer; Springer US
240 Páginas
Año de publicación: 2010-01-20
New York; NY; US
Impreso en
Idioma: Inglés
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
POD
XXIV, 240 p.

BB; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Crosstalk Avoidance; EDA; Noise Reduction; Off-Chip Communication; On-Chip Communication; VLSI; VLSI Design; VLSI Packaging; circuit design; construction; design automation; electronic design automation; integrated circuit; model; modeling; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Computer-Aided Design (CAD); EA; BC

On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford.
Presents a novel way to combine chip and package design, reducing cross-talk so that VLSI systems can be designed to operate significantly faster Provides a comprehensive set of bus cross-talk cancellation techniques, both memoryless and memory-based Offers a battery of approaches for a VLSI designer to use, depending on the amount of cross-talk their design can tolerate, and the amount of area overhead they can afford Includes supplementary material: sn.pub/extras
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